Answers Database
1_5.19 MAP: Incorrect warning message when ROC is used in VHDL design
Record #5461
Product Family: Software
Product Line: FPGA Implementation
Product Part: map
Problem Title:
1_5.19 MAP: Incorrect warning message when ROC is used in VHDL design
Problem Description:
It is suggested that VHDL customers who do not wish to have an external Global Reset signal to use a
ROC cell and connect all registers reset to this signal for the purpose of Functional and Timing Si
mulation of Global reset. When map identified the ROC cell it should quietly remove this net from t
he design. In a design in which the ROC is properly connected the following warning message is issu
ed:
WARNING:baste:21 - Chipcheck: The signal "GSRSimInt" is connected to the asynchronous set/reset of e
very flip-flop in the design. Using the dedicated GSR/GR (global set/reset) pin on the STARTUP comp
onent will reduce the ammount of routing resources required to implement the design. To use GSR/GR,
disconnect the "GSRSimInt" signal from the reset pin of every flip-flop in the design, and connec
t it to the GSR/GR pin of the STARTUP component. Note that all flip-flops on the device will be cle
ared when GSR/GR goes active.
Solution 1:
Since this signal, "GSRSimInt", is connected to a ROC cell, this message should not be issued since
it is the customers intention to optimize this signal. The warning message about connecting to the S
tartup component can be safely ignored.
End of Record #5461 - Last Modified: 01/22/99 16:14 |
