Answers Database
NC-VERILOG: Running simulation
Record #5474
Problem Title:
NC-VERILOG: Running simulation
Problem Description:
Urgency: Standard
General Description:
How to run simulation with NC-Verilog?
There are two methods to run simulation with NC-Verilog:
- Using library source files with compile-time options (similar to Verilog-XL)
- Using shared pre-compiled libraries
Please see (Xilinx Solution 2554) on how to compile the Alliance 2.1i
libraries for NC-Verilog.
Solution 1:
Using library source files with compile-time options (similar to Verilog-XL):
Depending on the makeup of the design (LogiBlox, Xilinx instantiated
primitives, or Coregen components), for RTL simulation, specify the
following at the command-line:
ncxlmode -y $XILINX/verilog/src/unisims -y $XILINX/verilog/src/simprims \
-y <path_coregen>/XilinxCoreLib +libext+.v $XILINX/verilog/src/glbl.v \
<testfixture>.v <design>.v
The $XILINX/verilog/src/unisims area contains the Unified components
for RTL simulation. The $XILINX/verilog/src/simprims area contains
generic simulation primitives for LogiBlox. The XilinxCoreLib area contains
the Coregen components for RTL simulation. Please see (Xilinx Solution 7859)
for instructions on extracting this library.
For timing simulation or post-Ngd2ver, the Simprims-based libraries are used.
Specify the following at the command-line:
ncxlmode -y $XILINX/verilog/src/simprims $XILINX/verilog/src/glbl.v \
+libext+.v <testfixture>.v <design>.v
Solution 2:
Using shared pre-compiled libraries:
Simulation Libraries have to be compield to <compiled_lib_dir> before
using NC-Verilog. See (Xilinx Solution 2554) for instruction on how to
compile the Xilinx Verilog libraries.
Depending on the makeup of the design (LogiBlox, Xilinx instantiated
primitives, or Coregen components), for RTL simulation, edit the hdl.var
and cds.lib to specify the library mapping.
# cds.lib
DEFINE unisims_ver <compiled_lib_dir>/unisims_ver
DEFINE simprims_ver <compiled_lib_dir>/simprims_ver
DEFINE xilinxcorelib_ver <compiled_lib_dir>/xilinxcorelib_ver
DEFINE worklib worklib
# hdl.var
DEFINE VIEW_MAP ($VIEW_MAP, .v => v)
DEFINE LIB_MAP ($LIB_MAP, <compiled_lib_dir>/unisims_ver => unisims_ver)
DEFINE LIB_MAP ($LIB_MAP, <compiled_lib_dir>/simprims_ver => simprims_ver)
DEFINE LIB_MAP ($LIB_MAP, <compiled_lib_dir>/simprims_ver => xilinxcorelib_ver)
DEFINE LIB_MAP ($LIB_MAP, + => worklib)
The unisims_ver area contains the Unified components for RTL simulation.
The simprims_ver area contains generic simulation primitives for LogiBlox. The
xilinxcorelib_ver area contains the Coregen components for RTL simulation. Please
see (Xilinx Solution 7859) for instructions on extracting this library.
After setting up the libraries, now compile and simulate the design:
ncvlog -messages -update $XILINX/verilog/src/glbl.v <testfixture>.v <design>.v
ncelab -messages testfixture_name glbl
ncsim -messages testfixture_name
The -update option of ncvlog enables incremental compilation.
For timing simulation or post-Ngd2ver, the Simprims-based libraries are used.
Specify the following at the command-line:
ncvlog -messages -update $XILINX/verilog/src/glbl.v <testfixture>.v time_sim.v
ncelab -messages -autosdf testfixture_name glbl
ncsim -messages testfixture_name
Please see (Xilinx Solution 947) on how to back-annotate the SDF file for timing
simulation.
End of Record #5474 - Last Modified: 11/12/99 17:16 |
