Answers Database
1.5i SP2 Bitgen -Bitstream for 4000X* and SpartanXL bitstream is incorrect for IFD with clock enable.
Record #5516
Product Family: Software
Product Line: FPGA Implementation
Product Part: bitgen
Product Version: 1.5i
Problem Title:
1.5i SP2 Bitgen -Bitstream for 4000X* and SpartanXL bitstream is incorrect for IFD with
clock enable.
Problem Description:
The bitstream for the xc4000XL(A) and SpartanXL IFD with a clock enable
is incorrect. The problem is that the IFD is clocking the new data in when
the enable is inactive. The problem seems to be that the clock enable
mux is using the feedback from the master latch instead of the slave latch.
Solution 1:
A fix for this problem is available in the 1.5i Service Pack2:
(Xilinx Solution #5887)
End of Record #5516 - Last Modified: 03/29/99 09:35 | 
