Answers Database
1.5i Virtex PAR - Placer seg faults when both list and single LOC csts applied to a TBUF set.
Record #5540
Product Family: Software
Product Line: FPGA Implementation
Product Part: par
Product Version: 1.5is1
Problem Title:
1.5i Virtex PAR - Placer seg faults when both list and single LOC csts applied to a TBUF
set.
Problem Description:
Design contains nets that are driven by two TBUFs. On each of these TBUF nets, one of the TBUFs is
LOC'ed to a single location on the right-side of the chip. List constraints are applied to the seco
nd TBUF and these constraints direct it towards the left-side of the chip. Placer core dumps during
the random drop initial placement.
Solution 1:
A fix for this problem is included in the 1.5i Service Pack 1. For details
on this Service Pack see http://www.xilinx.com/techdocs/5514.htm
End of Record #5540 - Last Modified: 02/20/99 19:10 |
