Answers Database
PAR misreports Virtex PCIIOBs as only inputs instead of bidirs.
Record #5541
Product Family: Software
Product Line: FPGA Implementation
Product Part: par
Product Version: 1.5i
Problem Title:
PAR misreports Virtex PCIIOBs as only inputs instead of bidirs.
Problem Description:
The code for automatic placement of SelectIO recognizes PCIIOBs as only inputs, when they may be bid
irectional I/Os. This can allow infeasible placements to be created because the output IO standard
of a PCIIOB may collide with the output standards of other IOBs placed in the same bank.
Solution 1:
A fix for this problem is included in the 1.5i Service Pack 1. For details
on this Service Pack see http://www.xilinx.com/techdocs/5514.htm
End of Record #5541 - Last Modified: 02/20/99 19:11 |
