Answers Database
M1.5i Virtex Timing - Timing Engine incorrectly propagates PERIOD thru 2 CLKDLLs in Virtex.
Record #5549
Product Family: Software
Product Line: FPGA Implementation
Product Part: Timing Analyzer
Product Version: 1.5i
Problem Title:
M1.5i Virtex Timing - Timing Engine incorrectly propagates PERIOD thru 2 CLKDLLs in Virtex.
Problem Description:
Urgency: Standard
General Description:
Using the Virtex DLL appnote, a 4x clock specification was
created. A NET PERIOD constraint was put on the clock pad
net. The PERIOD is adjusted through the first DLL correctly,
but is not adjusted for the second DLL. If gets the same value
as the first DLL.
Solution 1:
A fix for this problem is included in the 1.5i Service Pack 2. For details
on this Service Pack see http://www.xilinx.com/techdocs/5887.htm
End of Record #5549 - Last Modified: 05/20/99 10:26 |
