Answers Database
1.5i Virtex Back Annotation - Simulation errors during physical back annotation (no .ngm) due to clock renaming by map.
Record #5553
Product Family: Software
Product Line: FPGA Implementation
Product Part: map
Product Version: 1.5i
Problem Title:
1.5i Virtex Back Annotation - Simulation errors during physical back annotation (no .ngm)
due to clock renaming by map.
Problem Description:
The symptom is the mapper produces a GCLKIOB comp whose name ("clock") collides with its output sign
al name. When ngdanno tries to name the top level port/signal after the IOB comp, the name collisio
n is detected and that signal name is changed from "clock" to "clock_p". This causes the simulation
problem.
signal CLOCK : STD_LOGIC;
^
**Error: vhdlan,1072 rphy.vhd(108):
Illegal redeclaration of CLOCK.
I => CLOCK_P,
^
**Error: vhdlan,575 rphy.vhd(809):
CLOCK_P is not declared.
Logical (with mapped.ngm) worked OK.
Solution 1:
A fix for this problem is included in the 1.5i Service Pack 1. For details
on this Service Pack see http://www.xilinx.com/techdocs/5514.htm
End of Record #5553 - Last Modified: 02/20/99 20:33 |
