Answers Database
M1.5i - Ngdbuild : ERROR:basnu:192 - The LUT2_L symbol ... does not have any programming information
Record #5576
Product Family: Software
Product Line: FPGA Implementation
Product Part: ngdbuild
Product Version: 1.5is2
Problem Title:
M1.5i - Ngdbuild : ERROR:basnu:192 - The LUT2_L symbol ... does not have any programming
information
Problem Description:
Urgency: Standard
General Description:
When implementing a Virtex design synthesized by Synopsys FPGA/Design Compiler, The following error
may occur in ngdbuild:
ERROR:basnu:192 - The LUT2_L symbol "I_HDSL_TX/I_HDSL_TX_SP1/I_TX_GEN/add_4323/add_4323/A_LUT_13" do
es not have any programming information. The behavior of a LUT2_L symbol must be defined by an INIT
property or an EQN property.
This message means that the symbol (LUT2_L) that was inferred in the netlist does not have some of t
he program information that is defined using the INIT and EQN attributes.
Synopsys synthesis tool is not writing those attributes into the netlist.
Solution 1:
Do not use "uniquify" or "ungroup" in your run script. This is a known issue with uniquify, for mo
re info, see (Xilinx Solution 5048).
Solution 2:
Make sure that you are using the .synopsys_dc.setup file specifically designed for Virtex devices. T
his file can be found at:
$XILINX/synopsys/example/template.synopsys_dc.setup_virtex
Synopsys directives are used to specify the type of information to be exported to the netlist. Thes
e synthesis directives are defined in your Synopsys initialization file (.synopsys_dc.setup). For e
xample:
edifout_write_properties_list = {"INIT" "EQN"}
Solution 3:
Export your netlist in an SEDIF format <design.sedif>. You should not write out XNF or EDIF netlist
formats.
In FPGA/Design compiler synthesis script use the following command:
write -format edif -hierarchy -output TOP + ".sedif"
See (Xilinx Solution 5048) for more caveats about compiling HDL for Virtex designs using Synopsys co
mpilers.
End of Record #5576 - Last Modified: 07/22/99 11:36 |
