Answers Database LogiCORE PCI32 4000/Spartan: VHDL synthesis/simulation with PCI LogiCORE v2.0, Synplify 5.0.8, & M1.5i Record #5595 Product Family: Documentation Product Line: PCI Apps Product Part: PCI Design Solutions Problem Title: LogiCORE PCI32 4000/Spartan: VHDL synthesis/simulation with PCI LogiCORE v2.0, Synplify 5.0.8, & M1.5i Problem Description: Urgency: Standard General Description: The PCI LogiCORE v2.0 can be implementend in the VHDL synthesis/simulation flow in M1.5i using Synplify v5.0.8. For more information about the PCI LogiCORE, see http://www.xilinx.com/products/logicore/pci/pci_sol.htm. In this example, a design called 'ping' is used to demonstrate using the PCI LogiCORE v2.0 in this VHDL synthesis flow. In a 'real' design, the 'ping' design is replaced with the customer application. Note: it assumed that the user has already setup the environment for running M1.5i and Synplify 5.0.8. Synplify is not a HDL simulation tool. There is a VHDL simulation flow in M1.5i. When describing functional and timing simulation, a general flow will be described. For simulating the PCI LogiCORE v2.0 in M1.5i, use MTI or VSS. For this example, it is assumed that the user has already downloaded the PCI LogiCORE v2.0, and has unzipped the contents in a directory called 'pcim' in the root directory. If a target core had been downloaded, the directory created would have been 'pcis'. The PCI LogiCORE v2.0 contains files for a master, slave, and implementation files for the 4013XLT, 4028XLT, and 4062XLT. For this solution record, the 4013XLT is used and the PCI LogiCORE configured as a master is assumed. Solution 1: Functional simulation with the PCI LogiCORE v2.0 and M1.5i. (1) Get a list of files needed to functionally simulate the PCI LogiCORE. At the root directory of your system, type: cd c:\pcim\vhdl_exp\example\func_sim (2) The func_sim directory in the generic VHDL path (c:\pcim\vhdl\example\func_sim) will contain a file called analyze_ping, which lists the files neede d for functional simulation. The default list of files are located relative to the generic func_sim directory. The files needed for functional simulation are: ..\..\src\xpci\pci_lc_i.vhd -Simulation model for the PCI LogiCORE v2.0 ..\..\src\xpci\pcim_lc.vhd -Simulation model for the PCI LogiCORE v2.0 ..\source\cfg.vhd -Used for configuration of PCI LogiCORE v2.0 ..\source\ping.vhd -User application ..\source\pcim_top.vhd -Top-level file which connnects core to ping ..\source\dumb_target.vhd -signal generation for testbench ..\source\dumb_arbiter.vhd -signal generation for testbench ..\source\stimulus.vhd -signal generation for testbench ..\source\ping_tb.vhd -testbench For a user design, the ping.vhd file is replaced with the user VHDL code. At a minimum cfg.vhd, pcim_lc.vhd, and pci_lc_i.vhd must always be used. (3) Setup your VHDL simulator to use to the VITAL simulation library in M1.5i. The VITAL simulation library is located at %XILINX%\vhdl\src (4) Functionally simulate the PCI LogiCORE v2.0 by processing the list of files in step (2) into the VHDL simulator. Solution 2: Synthesis/Place & Route of the PCI LogiCORE v2.0 with Synplify v5.0.8 and M1.5.19 The PCI Core integration with the user application is a two step process. The user application is synthesized separately to create the corresponding xnf file, ping.xnf, in this case. The user application is then declared as a black   box in the top level, and synthesized along with the PCI Core to create the top-level xnf file. Both these xnf files are then used to run place and route. (1) To begin with, move into the C:\pcim\vhdl_exp\example\synthesis directory: cd C:\pcim\vhdl_exp\example\synthesis (2) Next, run the user application, ping. Create a new project in Synplify called ping.prj in the C:\vhdl_exp\example\synthesis directory. This is to run the user design, in this case, ping. Make sure of the following settings: * Include source file, ..\source\ping.vhd, by clicking on the Add button. Make the following settings on the "Set Device Options" menu by clicking on Change Target: * Set device target to one of the PCI supported devices. * Check "Disable I/O insertion"[The I/O pads will be inserted at the top level] * Set result format to xnf (3) Run ping.prj to create the result file, ping.xnf in the C:\pcim\vhdl_exp\example\synthesis directory. (4) Then next step is to run the top-level project. To do so, declare ping and pcim_lc as black boxes. Edit the C:\pcim\vhdl_exp\example\source\pcim_top.vhd to m ake the following change: * Add the following libraries at the top of the file: library xc4000; use xc4000.components.all; library synplify; use synplify.attributes.all; * Include the definition of the Unisim libraries within translate_on /off statements: -- synthesis translate_off library UNISIM; use UNISIM.VCOMPONENTS.ALL; -- synthesis translate_on * Define the component ping, as a black box. Insert this line after the component definition of ping: attribute black_box of ping : component is true; * Define the component pcim_lc as a black box, and declare the ports that have pads instantiated on them, as black box pad pins. Insert the following line after the component definition of pcim_lc: attribute black_box of pcim_lc : component is true; attribute black_box_pad_pin of pcim_lc : component is "AD_IO[31:0],CBE_IO[3:0],PAR_IO,FRAME_IO,IRDY_IO,TRDY_IO,STOP_IO, DEVSEL_IO,IDSEL_I,INTA_O,PERR_IO,SERR_IO,REQ_O,RST_I,GNT_I,PCLK" ; (5) Create a new project in Synplify to run the top level, called pcim_top.prj, in the C:\pcim\vhdl_exp\synthesis directory. Make sure of the following settings: * Add the following source files, in this order, to maintain hierarchical order: * cfg.vhd [or cfg_ping.vhd for Spartan] from the C:\pcim\vhdl_exp\example\source directory * pcim_top.vhd from the c:\pcim\vhdl_exp\example\source directory * Set the device target to one of the PCI supported devices[same as in ping.prj] * Make sure that the Result file is C:\pcim\vhdl_exp\example\synthes is\pcim_top.xnf * Make sure that "Disable I/O insertion" is not checked * Set result format to xnf. (6) Run the pcim_top.prj to create the result file, pcim_top.xnf (7) Edit the pcim_top.xnf file to remove the following line: PIN, CLKE, O, un15 (8) Copy the following files into the C:\pcim\vhdl_exp\example\synthesis directory: copy C:\pcim\vhdl_exp\src\xpci\pcim_lc.xnf C:\pcim\vhdl_exp\example\synthesis\pcim_lc.xnf copy C:\pcim\vhdl_exp\src\xpci\pci_lc_i.ngo c:\pcim\vhdl_exp\example\synthesis copy C:\pcim\vhdl_exp\ucf\m13xp240.ucf C:\pcim\vhdl_exp\example\synthesis copy C:\pcim\vhdl_exp\src\guide\m13xp240.ncd C:\pcim\vhdl_exp\example\synthesis pcim_lc.xnf must always be used. This file merges the core with the design correctly and contains needed constraints. pci_lc_i.ngo is the PCI LogiCORE v2.0 design. A constraint file included with the PCI LogiCORE v2.0 must be used. There are four constraint files in the C:\pcim\vhdl_exp\src\ucf directory. There are two UCF files for the 4013XLT, one for the 4028XLT, and three for the 4062XLT. The 4013xltpq240 guide file was used in this example. (9) Place and route the design by running the following commands in the C:\pcim\vhdl_exp\example\synthesis directory. Optionally, the listed commands below can be placed in a batch file: set XIL_MAP_LOC_CLOSED=true ngdbuild -p 4013xlpq240-1 -uc C:\pcim\vhdl_exp\example\synthesis\m1 3xp208.ucf pcim_top.xnf map pcim_top.ngd -o pcim_top.ncd pcim_top.pcf par -gm exact -gf c:\mypci\m13xp240.ncd -l 4 -d 1 -w pcim_top pcim _top_routed pcim_top trce -v 10 pcim_top_routed pcim_top ngdanno pcim_top_routed ngd2ver -w pcim_top_routed Solution 3: Timing Simulation with the PCI LogiCORE v2.0 and M1.5i. (1) After place and route, a structural VHDL file, pcim_top_routed.vhd, and an SDF file, pcim_top_routed.sdf, will be in the C:\pcim\vhdl_exp\example\synthesis directory. (2) Setup your VHDL simulator to use the M1.5i VHDL simulation libraries, which are located in %XILINX%\dl\src. (3) Simulate the PCI LogiCORE design, by reading in the pcim_top_routed.vhd file, pcim_top_routed.sdf file, and testbench file into the VHDL simulator. In this case for the ping design, the 'testbench' is comprised of the following files: c:\pcim\vhdl_exp\example\source\ping_tb.vhd c:\pcim\vhdl_exp\example\source\stimulus.vhd c:\pcim\vhdl_exp\example\source\dumb_target.vhd c:\pcim\vhdl_exp\example\source\dumb_arbiter.vhd End of Record #5595 - Last Modified: 10/01/99 14:21

For the latest news, design tips, and patch information on the Xilinx design environment, check out the Technical Tips!