Answers Database
M1.5i Virtex VHDL simprim model incorrect for SRL16, SRL16_1, SRL16E, and SRL16E_1 models
Record #5609
Product Family: Software
Product Line: Merged Core
Product Part: simprims
Problem Title:
M1.5i Virtex VHDL simprim model incorrect for SRL16, SRL16_1, SRL16E, and SRL16E_1 models
Problem Description:
Urgency: Standard
General Description:
The VHDL simprim models for M1.5i incorrectly simulate the SRL16,
SRL16_1, SRL16E, and SRL16E_1 models. The problem is found in the
address pins on the shift register. The pins are simulated in reverse
order. For example, if you assign A3=1, A2=0, A1=0, and A0=0, which is
a 9-bit stage, it is not and is really a 2-bit stage and the pins are
A3=0, A2=0, A1=0, and A0=1.
Solution 1:
The VHDL library needs to be modified. The file is found at:
<XILINX>/vhdl/src/simprim_VITAL.vhd.
Make the following modification to the SRL16 model:
ADDRESS := (A3_ipd, A2_ipd, A1_ipd, A0_ipd);
...
if (VALID_ADDR) then
LENGTH := SLV_TO_INT(ADDRESS);
else
....
where ADDRESS is defined as std_logic_vector(3 downto 0);
The vhd file will need to be re-compiled for the changes to take
effect.
This is fixed in Xilinx 2.1i
End of Record #5609 - Last Modified: 06/26/99 08:28 |
