Answers Database
1.5i PAR - Virtex design with apparently good RPM fails during placement.
Record #5616
Problem Title:
1.5i PAR - Virtex design with apparently good RPM fails during placement.
Problem Description:
ERROR:xvkap:53 - RLOC constraints have been applied to a subset of the slices
in the carry chain containing the slice H14/U10/uc_sm<0>. RLOCs must either
be applied to every slice in a carry chain or none of the slices in a carry
chain.
This problem may be occuring because of non-carry logic driven by Cout at the end of the carry
chain. Map creates a Cout -> Cin route-thru to reach the non-cary logic. The result is an extra
segment to the carry chain that is not RLOC'd. PAR balks at the placement because it can not
handle a partially RLOC'd carry chain.
Is this a DUP of 110634?
Solution 1:
The work around is to include the non-carry load to the macro and RLOC it so that it is next to
the end of the original carry chain.
A fix for this problem is planned for M2.1.
End of Record #5616 - Last Modified: 02/08/99 17:36 | 
