Xilinx Answer #5630 : V1.5.2 COREGEN: Information on the Coregen v1.5.2 release shipped with F1.5i_sp1/sp2, and A1.5i_sp1/sp2 (Service Pack 1 and 2 for Foundation F1.5i or Alliance A1.5i).

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V1.5.2 COREGEN: Information on the Coregen v1.5.2 release shipped with F1.5i_sp1/sp2, and A1.5i_sp1/sp2 (Service Pack 1 and 2 for Foundation F1.5i or Alliance A1.5i).

Record #5630
Product Family: Software

Product Line: Coregen

Product Part: Coregen

Product Version: c1_5

Problem Title:

V1.5.2 COREGEN: Information on the Coregen v1.5.2 release shipped with F1.5i_sp1/sp2, and A1.5i_sp1/sp2 (Service Pack 1 and 2 for Foundation F1.5i or Alliance A1.5i).

Problem Description:
Urgency: standard

General Description:
Information on the Coregen v1.5.2 shipped with Foundation and
Alliance 1_5i Service Packs 1 and 2.

Solution 1:

The Coregen v1.5.2 update is packaged as follows with the following M1_5i
Service Pack 1 updates:

- Foundation 1_5i Service Pack 1: coregen_upd.exe - Alliance 1_5i Service Pack 1 for PC's: 15i_sp1_cgen_ws.tar.gz - Alliance 1_5i Service Pack 1 for Workstations: 15i_sp1_cgen_ws.tar.gz

REQUIREMENTS: The Coregen updates in the 1_5i Service Packs above
are incremental updates and must be installed over existing Coregen v1.5.0
installations.

Please note that these updates are SOFTWARE-ONLY updates. New
COREs are available on the Xilinx CoreLINX web page:

    http://www.xilinx.com/products/logicore/coregen/corelinx.htm

BUGS FIXED:

CR 108040:
"Warning 9199: Unknown component - B998, TBUF" when loading design
containing CoreGEN Sine-Cosine LUT, FIFO, ROM, or RAM components into
the F1.5 Foundation simulator.

(Xilinx Solution 4521)

CR 106196:
V1.5.x COREGEN, NGDBUILD, (VIRTEX BLOCK RAM): "ERROR: BASNB
Pin mismatch".
COREGEN does not allow you to select the netlist bus delimiter format if one of your selections is VHDL or Verilog Instantiation Template.

(Xilinx Solution 4041)

In addition, a number of datasheets have been updated in this incremental
update, including:

- Synchronous FIFO - improved timing diagram)
- SDA FIR Filter - added description of calculation of output bit width
- PDA FIR Filter - (CR 107205, 4KXL-08 speed data, description of c_m_o[n:0]
                      and c_d_o[n:0] output pins,
- Dual Port Block RAM - added description of MIF files required for initialization
                      of Virtex block RAM in HDL behavioral simulation
                      (Xilinx Solution 5218)

End of Record #5630 - Last Modified: 03/26/99 17:42

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