Xilinx Answer #5633 : FPGA Express: Syntax error at or near token 'bxx (VE-0)

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FPGA Express: Syntax error at or near token 'bxx (VE-0)

Record #5633
Product Family: Software

Product Line: Synopsys

Product Part: FPGA Express

Product Version: 3.1

Problem Title:
FPGA Express: Syntax error at or near token 'bxx (VE-0)

Problem Description:
Urgency: Standard

General Description: Express produces an error when the user
either synthesizes or checks syntax:

Error: syntax error at or near token 'bxx (VE-0)

where xx is some number. The line in question is using a `define
in Verilog to set the width of a wire or reg as shown:

data = `DATA_BUS_WIDTH'b0;

where there exists:

`define DATA_BUS_WIDTH 14

Solution 1:

This particular syntax is not supported by Synopsys compilers.
The user must replace the width specification by a number.
For example:

data = 14'b0;

End of Record #5633 - Last Modified: 03/15/99 14:31

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