Answers Database
FPGA Express: Inserts OBUF when instantiating OBUFE in HDL design
Record #5682
Product Family: Software
Product Line: Synopsys
Product Part: FPGA Express
Product Version: 3.1
Problem Title:
FPGA Express: Inserts OBUF when instantiating OBUFE in HDL design
Problem Description:
Urgency: Standard
General Description: After instantiating an OBUFE in an HDL design, FPGA Express
will also place an OBUF after the OBUFE and cause multiple drivers errors during
the Translate phase of implementation (NGDBUILD).
Solution 1:
Infer the functionality of the OBUFE. For example:
VHDL:
DOUT <= DATA when ENABLE='1' else 'Z';
Verilog:
assign DOUT = ENABLE ? DATA : 1'bZ;
Solution 2:
Instantiate an OBUFT and invert the signal that is used for the T pin.
End of Record #5682 - Last Modified: 07/12/99 14:04 |
