Answers Database
Virtex: How to use BlockRams in HDL codes
Record #5693
Product Family: Hardware
Product Line: Virtex
Product Part: Virtex General Hardware
Problem Title:
Virtex: How to use BlockRams in HDL codes
Problem Description:
Urgency: Standard
Problem Descriptions:
How to use BlockRams in HDL codes for Virtex designs.
Solution 1:
BlockRams currently can't be inferred by any synthesis tools. They must
be instantiated in the HDL codes. This solution record provides Verilog
and VHDL examples of instantiating a synchronous 512x8 BlockRAM.
NOTE: the Data input must be declared as a bus even if the BlockRam
is configured as one bit wide.
Verilog example:
module ram512x8 (WE,EN,RST,CLK,ADDR,DI,DO);
input WE,EN,RST,CLK;
input [7:0] DI;
input [8:0] ADDR;
output[7:0] DO;
RAMB4_S8 U0 (.WE(WE), .EN(EN), .RST(RST), .CLK(CLK), .ADDR(ADDR), .DI(DI), .DO(D
O));
endmodule
Solution 2:
VHDL example:
library ieee;
use ieee.std_logic_1164.all;
entity ram512x8 is
port (
WE, EN, RST, CLK : in std_logic;
DI : in std_logic_vector (7 downto 0);
ADDR : in std_logic_vector (8 downto 0);
DO : out std_logic_vector (7 downto 0));
end ram512x8;
architecture ram_arch of ram512x8 is
component RAMB4_S8 port (
WE, EN, RST, CLK : in std_logic;
ADDR : in std_logic_vector (8 downto 0);
DI : in std_logic_vector (7 downto 0);
DO : out std_logic_vector (7 downto 0));
end component;
begin
U0 : RAMB4_S8 port map (
WE=>WE,
EN=>EN,
RST=>RST,
CLK=>CLK,
DI=>DI,
ADDR=>ADDR,
DO=>DO);
end ram_arch;
End of Record #5693 - Last Modified: 04/06/99 09:26 |
