Answers Database
1.5i 4KXL PAR - 4036xl design unable to place some CLBs clocked by BUFGE
Record #5704
Product Family: Software
Product Line: FPGA Implementation
Product Part: par
Product Version: 1.5i
Problem Title:
1.5i 4KXL PAR - 4036xl design unable to place some CLBs clocked by BUFGE
Problem Description:
A case has been seen where some CLBs were being driven by two different
BUFGLEs. One BUFGLE was driving the clock pin and another was driving a
non-clock pin. The result was conflicting implicit constraints that were attempting
to place the CLB in the same quadrant as both BUFLE's.
WARNING:Place - Unable to find location. CLB component IFFTRDN not placed.
WARNING:Place - Unable to find location. CLB component U34/RELPUL1 not placed.
WARNING:Place - Unable to find location. CLB component U46/U47/$I518/$1I148
not placed.
WARNING:Place - Unable to find location. CLB component ACTIVE not placed.
WARNING:Place - Unable to find location. CLB component U46/U47/$I518/$1I146
not placed.
WARNING:Place - Unable to find location. CLB component U46/U47/CAR0 not
placed.
ERROR:Place - There were not enough sites to place all selected components
Finished initial Placement phase. REAL time: 39 secs
Solution 1:
This problem has been assigned to be fixed in the as yet unnamed release
following version 2.1i. Meanwhile, the work around is to replace BUFGLE's
with BUFGLS's.
End of Record #5704 - Last Modified: 05/19/99 09:55 |
