Answers Database
LogiCORE PCI: Can the top-level of hierarchy be modified in a Xilinx PCI design?
Record #5705
Product Family: Documentation
Product Line: PCI Apps
Product Part: PCI Frequently Asked Questions
Problem Title:
LogiCORE PCI: Can the top-level of hierarchy be modified in a Xilinx PCI design?
Problem Description:
Priority: Standard
Problems Description:
Can the PCI design be used in such a way that the PCIM_TOP.HDL
is not the uppermost level of hierarchy? Additionally, can the PCIM_TOP
name be changed?
Solution 1:
When the Xilinx supplied PCI design guide file is viewed in the FPGA_EDITOR,
it clearly shows the Xilinx implementation tools will start looking for a signal name
match from a PCI_CORE/PCI_LC level. Any levels of hierarchy can be added or
renamed above the PCI_CORE instance name.
However, this approach may not work if any of the paths to I/O pads are guided.
Addiing a level of hierarchy or renaming the top level file will cause the guide
file to break. The guide file will then have to be changed manually to reflect that
change. Please contact the Xilinx Design Services for such modifications.
Solution 2:
NCDREAD will also report the number of COMPS that are guided on
the third line of its report. This number can be compared with the
first number mentioned in the *.par report on the following line of it:
Placed 101 out of 666 comps in the new design.
In order to find this message, just do a search on "comps" in your
*.par report. The two numbers will be identical if the guide file was
completely used.
End of Record #5705 - Last Modified: 11/04/99 11:29 |
