![]() |
|
![]() |
|
Answers Database
FPGA / Design Compiler 1999.05: Using SYNLIBS settings produces warning UISN-26
Record #5706
Product Family: Software link_library = {xprim_s20xl-4.db xprim_spartanxl-4.db xgen_spartanxl.db xfpga_spartanxl-4.db
xio_spartanxl-4.db xdw_spartanxl.sldb} /* <---- the library is added here */
target_library = {xprim_s20xl-4.db xprim_spartanxl-4.db xgen_spartanxl.db xfpga_spartanxl-4.db
xio_spartanxl-4.db}
define_design_lib xdw_spartanxl -path
/home/davidd/synopsys/synlib/syn9802/synopsys/libraries/dw/lib/spartanxl
symbol_library = {spartanxl.sdb}
synthetic_library = {xdw_spartanxl.sldb standard.sldb}
End of Record #5706 - Last Modified: 11/17/99 15:22 |
| For the latest news, design tips, and patch information on the Xilinx design environment, check out the Technical Tips! |