Answers Database
pld_men2edif ERROR:basnu:120 - logical net "port_signal_name" has multiple pad connections
Record #5713
Product Family: Software
Product Line: Mentor
Product Part: pld_men2edif
Problem Title:
pld_men2edif ERROR:basnu:120 - logical net "port_signal_name" has multiple pad connections
Problem Description:
Urgency: Standard
General Description:
I am trying to run pld_men2edif but when I run it I am getting the following error:
ERROR:basnu:120 - logical net "port_signal_name" has multiple pad connections
What could be causing this?
Solution 1:
This error could result when running pld_men2edif, when there are special ports such as
TDO, MD0, MD1, TDI, etc used in the schematic for user I/O after configuration, and a
symbol was created for a Board Level Simulation where the symbol has a pin on it the
same name as the signal name going to the special PORT pad (ie. TDO).
It is easily understandable why users would want to have the signal going to the TDO
pin for user I/O to goto the symbol pin, for Board Level Simulation. The problem arises
because the TDO pad is special, as well as MD0, MD1, etc. Normally for IPAD's and
OPAD's when pld_men2edif is run, the PAD's are not written into the EDIF netlist, as
it is not required. Running pld_men2edif will translate the signal going to the PAD, to
a 'port' in the netlist so that the Xilinx tools will be able to determine if this goes to an
iopin or not. For special pins like TDO the specific pad must be written into the netlist
in order for the Xilinx tools to be able to realize that this particular signal going to the
TDO in the schematic must only goto the TDO pin on the package.
When a symbol resides under the top level schematic EDDM in which this symbol
does contain a pin for the signal going to the TDO pad, pld_men2edif will create
a netlist that has essentially two ports driving a single buffer. One going to a 'port'
in the netlist, and the other going to the TDO pad in the same netlist.
You may be asking, "Why does pld_men2edif complete without errors for my top level
schematic that only has IPAD's and OPAD's?", even though I do have a symbol created
for a Board Level Simulation with these signals going to pins. The reason this works
is there is a property called CLASS=P on IPAD's and OPAD's, which causes
pld_men2edif to not write the IPAD and OPAD elements into the resulting EDIF netlist,
and to write 'port' statements for them instead. The CLASS=P property also makes the
signal hierarchial, which is why the symbol for the top level schematic can contain pins
for the signals going to all the IPAD's and OPAD's. Due to the nature of the property
the CLASS=P property can not be used on special pins such as TDO, as this will
results in a multiple drivers error.
NOTE: This will not be a problem for a Baord Level Timing Simulation, and only
arises for a Board Level pre-M1 Functional Simulation.
Solution 2:
There are a few way to workround this problem invovling a little work from the
user, and he/she must be careful to keep things in sync.
1) maintain two seperate designs, one for implmentation, and one for functional board
level sim. Within 1) there are two ways to do this a) add a portout to the existing
schematic in parallel with the TDO b) add an OPAD in parallel to the TDO. Making sure
in both ot the above the symbol for the board schematic exists only in the functional
sim design. The Board Level schematic viewpoint can then point to the 'copy' of the
design. Any design changes will have to be updated in the 'copy' though.
2) Create a symbol in the functional board level sim directory, that represents the chip.
Then create a new empty sheet under this and copy and paste only the top level sheet
of the chip design, and paste this into the new empty sheet. Now THIS schematic will
have to be modified as in 1), but will leave the original design untouched for implmentation.
Any design changes in the original top level schematic will have to be updated in the Board
Level Simulation top level schematic too.
End of Record #5713 - Last Modified: 02/22/99 17:08 |
