Answers Database
Virtex JTAG - How to program multiple Virtex devices in a JTAG chain
Record #5718
Product Family: Hardware
Product Line: Virtex
Product Part: Virtex General Hardware
Problem Title:
Virtex JTAG - How to program multiple Virtex devices in a JTAG chain
Problem Description:
urgency: standard
general description:
If multiple Virtex devices are connected in a JTAG daisy-chain (where
TDO of one device connects to TDI of another device, and all the TCK's
conneceted as togethere as one TCK, and all the TMS pins are connected
as one TMS pin, it is possible to configure this entire daisy chain via the
Virtex JTAG pins. There are software and hardware procedures
to follow to make this happen.
Solution 1:
First, prepare the Virtex bitstreams for JTAG configuration.
For each bitstream in the Virtex daisy-chain, create the .bit file
using the following command-line:
bitgen -g startupclk:jtagclk designName.ncd
Where designName.ncd is the name of the routed ncd file from par.
If you do not do this the Virtex device will accept the bitstream,
DONE will be high and /INIT will be high, but the device will not
respond to stimulus. This option tells the Virtex device to use the
clocks on the TCK pin to finish the JTAG configuration process.
If you do not wish to use the TCK to clock the startup sequence
then you must use the STARTUP_VIRTEX symbol to attach a specific
internal clock net to be used for the startup sequence. Bitgen must
then be instructed to use the userclk for startup with the option -g:userclk
If you are configuring a Virtex device via JTAG only after power-up,
then you must set the mode pins of the Virtex device to 101
(M2=1,M1=0,M0=1 NOPULLUPS) or 001 (M2=0,M1=0,M0=1 PULLUPS).
If you do not set the mode pins to 101 or 001 before power-up, and then
enter a configure instruction, the Virtex device may not configure reliably.
Second, now take your bit files into the JTAG Programmer software to complete
the configuration. If you are using your own software, then read on.
The devices in the daisy-chain are configured one at
a time using the following steps:
(a) Load CFG_IN instruction into the 1st device
(and BYPASS in all downstream devices).
(b) Shift in 1st bitstream with no leading zeros.
(c) Go through Test-Logic-Reset (TLR).
(d) Load BYPASS in the 1st device and CFG_IN in the 2nd
device (and BYPASS in all downstream devices).
(e) Shift in 2nd bitstream with 31 leading zeros.
(f) Go through TLR.
Repeat d through f for each successive device reducing
the number of leading zeros by one for each device prior to the one
being configured.
g) Load the JSTART command into all devices.
h) Go to Shift-DR and clock TCK 10 times.
All devices should be active at this point.
Solution 2:
Troubleshooting the JTAG Configuration of an Individual Virtex Device
Note that the TAP is always active on Virtex devices and can be used
for troubleshooting. In JTAG configuration mode, DONE functions exactly
as it does in non-JTAG configuration mode. While in JTAG configuration
mode with Virtex, the DONE pin can be monitored to see if the bitstream
has been successfully loaded into the device. If DONE is low three things
are possible: the entire bitstream hasn't been sent, the entire bitstream
has been sent but the startup sequence has not finished, or an error has
happened. If DONE goes high, this means that the Virtex device has
received the entire bitstream and that the bitstream was not
corrupted.
If DONE has not gone high , the bitstream has been created with
the -g option for jtagclk, and the JSTART instruction has been
executed, it is possible that an error in the bitstream was detected.
In non-JTAG configuration of a Virtex device, this sort of failure is
revealed via the /INIT pin. In Virtex JTAG configuration, the external
/INIT pins not used for reporting status. It is possible to view the
internal /INIT signal. After finishing a Virtex JTAG configuration where
the DONE pin stays low, do the following to see if an error in the
bitstream was detected:
(a) Move the TAP to the test-logic-reset state.
(b) Load the CFG_IN instruction.
(c) go to the Shift-DR state and shift in this 64-bit pattern:
2 8 0 0 E 0 0 1 0 0 0 0 0 0 0 0
0010 1000 0000 0000 1110 0000 0000 0001 0000 0000 0000 0000 0000 0000 0000 0000
^
|
Shift in data starting from this bit.
(d) Load the CFG_OUT instruction.
(e) go to Shift-DR and clock TCK 32 times while reading TDO.
The data is the contents of the STATUS register. The last bit out will be
a 1 if there was a CRC error. After a successful configuration the 32 bits
would normally be:
0000 0000 0000 0000 0 1 1 111 1 1 0 1 0 1111 0
^
|
CRC_ERROR bit
The rightmost bit is the last one shifted out. If the returned values deviates
from the above there may be a problem with your configuration.
End of Record #5718 - Last Modified: 01/10/00 21:55 |
