Answers Database
1.5i Virtex Map - Bus error (core dumped) on V300 design
Record #5736
Product Family: Software
Product Line: FPGA Implementation
Product Part: map
Product Version: 1.5is1
Problem Title:
1.5i Virtex Map - Bus error (core dumped) on V300 design
Problem Description:
Urgency: Normal
General Description:
m1.5.28 virtex 300 design. synplicity 5.08.
When running map with -pr b option (pack both input/output registers in IOB),
map exits with bus error (core dumped) as follows:
M1_5.28: zeppelin% map -pr b -o tx_fpga_map.ncd tx_fpga.ngd
map: version M1.5.28i
Copyright (c) 1995-1998 Xilinx, Inc. All rights reserved.
Reading NGD file "tx_fpga.ngd"...
Using target part "v300bg432-4".
Processing logical timing constraints...
..Removing unused or disabled logic...
Checking design components...
Optimizing...
Pushing bubbles ...
Collapsing logic...
Merging...
Bus Error (core dumped)
Solution 1:
workarounds:
1. run map with -pr o (pack registers in IOB output register)
2. run map without -pr option (no greedy packing of registers into IOBs)
This issue has been fixed in version 2.1i.
End of Record #5736 - Last Modified: 06/26/99 16:36 |
