Answers Database
FPGA Express 3.2: Verilog pre-processor available to allow 'ifdef, 'else, and 'endif
Record #5791
Product Family: Software
Product Line: Synopsys
Product Part: FPGA Express
Product Version: 3.2
Problem Title:
FPGA Express 3.2: Verilog pre-processor available to allow 'ifdef, 'else, and 'endif
Problem Description:
Urgency: Standard
General Description:
FPGA Express 3.2 now has a Verilog Pre-processor that allows the use of the following directives:
'ifdef
'else
'endif
`define macros with and without arguments
This pre-processor is not enabled automatically, so users will have to set a switch to turn it on.
It is not turned on by default because when it is on it will ignore the //synopsys translate_off
compiler directive.
Solution 1:
To enable this feature, select Synthesis -> Options and set the proper option.
In standalone FPGA Express, check the box next to:
"Enable Verilog Pre-processor"
In the Foundation Project Manager, select "Enable" under the option:
"Verilog 'ifdef support"
End of Record #5791 - Last Modified: 08/09/99 12:12 |
