Answers Database
1.5i SP2 Virtex Map - Cannot satisfy LOC/RLOC constraint for CC8CE and FDRSE design
Record #5835
Product Family: Software
Product Line: FPGA Implementation
Product Part: map
Product Version: 1.5i
Problem Title:
1.5i SP2 Virtex Map - Cannot satisfy LOC/RLOC constraint for CC8CE and FDRSE design
Problem Description:
Urgency: Standard
General Description: When creating a schematic with an CC8CE
(8-bit counter using carry chain with clear and enable) the
design runs fine. However, when changing the FFS in the
counter to FDRSE, MAP errors out.
FATAL_ERROR:xvkma:xvkmapper.c:1691.1.112 - Cannot satisfy
LOC/RLOC constraint on comp $I1/$1I285 Process will terminate.
Please call Xilinx support.
Solution 1:
A fix for this problem is included in 1.5i Service Pack 2. For more information see:
(Xilinx Solution #5887)
End of Record #5835 - Last Modified: 03/29/99 09:42 |
