Xilinx Answer #5840 : 1.5i SP2 Virtex Bitgen - Virtex progammable clock delay support added for use with PCI 66 MHz designs.

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1.5i SP2 Virtex Bitgen - Virtex progammable clock delay support added for use with PCI 66 MHz designs.

Record #5840
Product Family: Software

Product Line: FPGA Implementation

Product Part: bitgen

Product Version: 1.5i

Problem Title:

1.5i SP2 Virtex Bitgen - Virtex progammable clock delay support added for use with PCI 66 MHz designs.

Problem Description:

PCI 66 MHz designs need to use the progammable clock delay to meet 66 MHz timing. Testing has show n the need to use this progammable delay with independent control for each clock

Solution 1:

This feature is now available in the 1.5i Service Pack2:

(Xilinx Solution #5887)

End of Record #5840 - Last Modified: 03/29/99 09:41

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