Answers Database
1.5i SP2 Virtex MAP - Map does not correctly pack FMAPs when using CORE_LUT_CONSTRAINT
Record #5841
Product Family: Software
Product Line: FPGA Implementation
Product Part: map
Product Version: 1.5i
Problem Title:
1.5i SP2 Virtex MAP - Map does not correctly pack FMAPs when using CORE_LUT_CONSTRAINT
Problem Description:
MAP packs LUT primitives correctly with CORE_LUT_CONSTRAINT but does not pack FMAPs correctly. The
packing of FMAPed logic is the main reason CORE_LUT_CONSTRAINT was requested. This is critical for
guide file design (PCI 66 MHz).
Solution 1:
A fix for this problem is available in the 1.5i Service Pack2:
(Xilinx Solution #5887)
End of Record #5841 - Last Modified: 03/29/99 09:41 | 
