Answers Database
1.5i Virtex Map - MAP is dropping some FF paths from Period constraint.
Record #5889
Product Family: Software
Product Line: FPGA Implementation
Product Part: map
Product Version: 1.5is1
Problem Title:
1.5i Virtex Map - MAP is dropping some FF paths from Period constraint.
Problem Description:
Urgency: Standard
Problem Description:
On Virtex design Worst case paths are not always covered by the PERIOD constraint.
Solution 1:
MAP is dropping some FFS from the timing groups. Hence under
timing analysis worst case path is not always shown.
A work around is to use a FFS to FFS constraint instead.
This problem is fixed for the 2.1i release scheduled to be released
in June, 1999.
Solution 2:
Do custom timing analysis in the Timing Analyser to cover the FFs to FFs path.
Solution 3:
The missing paths may not just be FF to FF but can also
be from FFs to BlockRams. So the period timespec has to be
replaced by 4:
From:To's - FF->FF, FF->Ram, Ram->FF,
Ram->Ram. Although this can be
reduced to 1 timespec with some use of time groups.
Also the period spec always has lower priority than
from:to so when you replace it you need to start using explicit
PRIORITY values to preserve multicycle from:to definitions.
In 1.5i the priority scheme is: tig, from:to, and period.
In 2.1i the priority scheme is: tig, from:thru:to, from:to, offset, and then period.
Solution 4:
Add the missing entries to the PCF file time groups so that these paths are considered by PAR.
End of Record #5889 - Last Modified: 10/13/99 11:52 |
