Answers Database
Virtex Timing: What is the CLKA -> CLKB setup time for different ports (Tbccs) timing parameter?
Record #5894
Product Family: Hardware
Product Line: Virtex
Product Part: V300
Problem Title:
Virtex Timing: What is the CLKA -> CLKB setup time for different ports (Tbccs) timing
parameter?
Problem Description:
Urgency: Standard
General Description: In the Virtex data sheets, what does the
BlockRAM timing parameter 'CLKA -> CLKB setup time for
different ports (Tbccs)' actually mean?
Solution 1:
Imagine the following scenario:
Using Dual-port BlockRAM where both clocks are completely independent
of each other. The design requires a WRITE on one port and a READ from
the same address on the other port.
This timing parameter (Tbccs) is the minimum amount of time required
between the two clock edges to guarantee the correct data will
appear on DOUT.
End of Record #5894 - Last Modified: 03/15/99 15:25 |
