Answers Database
1.5i Timing - PAR appears to hang due to problem with OFFSET constraint.
Record #5918
Product Family: Software
Product Line: FPGA Implementation
Product Part: par
Product Version: 1.5is1
Problem Title:
1.5i Timing - PAR appears to hang due to problem with OFFSET constraint.
Problem Description:
URGENCY: hot
GENERAL DESCRIPTION:
PAR and other applications doing timing analysis may appear to be hung when an OFFSET constraint is
evaluated against and INFF residing in the same clock IOB as the intended clock network.
Solution 1:
The incorrect timing behavior results because a buffer and FF is used in
the same clock IOB. This can be avoided by moving the FF out of the
clock IOB.
In schematic, instead of using the IFD component, use the IBUF and FD component.
In HDL, in the Constraints Editor, for the impeding clock signal, select IOB reg = FALSE.
A software fix for this problem will be available in the 2.1i release due to be shipped in June, 199
9.
End of Record #5918 - Last Modified: 04/09/99 15:48 |
