Answers Database
LogiCORE PCI64 Virtex (v3.0): 66 MHz implementation issues
Record #5989
Product Family: Documentation
Product Line: PCI Apps
Product Part: PCI Frequently Asked Questions
Problem Title:
LogiCORE PCI64 Virtex (v3.0): 66 MHz implementation issues
Problem Description:
Urgency: Standard
General Description:
Are there any special considerations that should be taken into account while
designing a 66MHz PCI interface?
Solution 1:
For most 66 MHz designs, bitgen must be run with a special option to change the behavior of a
global clock buffer used in the design. When you are ready to generate a
bitstream for a 66 MHz design, run bitgen with the following option:
bitgen -g Gclkdel3:00100 pcim_top_routed.ncd [XCV300-6]
bitgen -g Gclkdel3:00100 pcim_top_routed.ncd [XCV300E-6]
bitgen -g Gclkdel3:11111 pcim_top_routed.ncd [XCV1000-6]
bitgen -g Gclkdel3:11111 pcim_top_routed.ncd [XCV1000E-6]
This option is used to introduce additional delay on a global clock net. For
66 MHz designs, it is important to note that this additional delay is observable
on the CLK output of the LogiCORE PCI64 interface, which is supplied to the
user application. Timing constraints for the user application must be
generated with this in mind. The place and route tools are not aware of this
additional delay because it is added as a bitstream post-processing step.
Consult the user constraint file for examples of how to account for this delay
when generating timing specifications.
This option must not be used for 33 MHz designs.
Solution 2:
Note that the example design is, by default, configured as a 66 MHz design. Due
to the increased difficulty of 66 MHz designs, the example design may fail to meet
the timing specifications for the period constraint on the first cost table (seed) used
during place and route. Consult the Xilinx Alliance or Xilinx Foundation
documentation to learn how to change the cost table, or to use multiple cost tables.
If you are attempting a 33 MHz design, follow the instructions in the LogiCORE
PCI64 Virtex Implementation Guide to change the implementation flow. The
example design, when run at 33 MHz, easily meets all timing constraints.
End of Record #5989 - Last Modified: 11/02/99 14:31 |
