Answers Database
V2.1i COREGEN, C_IP2: Latency may be incorrect in Virtex Variable Multiplier VHDL behavioral model
Record #6012
Product Family: Software
Product Line: LogiCore
Product Part: Coregen IP Modules
Problem Title:
V2.1i COREGEN, C_IP2: Latency may be incorrect in Virtex Variable Multiplier VHDL
behavioral model
Problem Description:
Urgency: standard
General Description:
The number of cycles of latency modeled by the VHDL behavioral model for the
Virtex Variable Multiplier shipped in C_IP2 may be incorrect.
For example, a multiplier with an 8-bit B input and both pipeline and output registers
is shows a latency of only one clock cycle in simulation. The correct number of cycles is
3 for this case, as indicated in the multiplier datasheet.
Solution 1:
To work around this problem, you can do a post-NGDBUILD functional simulation
instead of a direct behavioral simulation using the CORE Generator models. Refer
to the datasheet for this module for information on the correct number of cycles of latency for
multiplier implementation.
End of Record #6012 - Last Modified: 10/29/99 16:45 |
