Answers Database 2.1i COREGEN, MTI, VHDL: Required MTI commands for analyzing/compiling the CORE Generator VHDL models Record #6037 Product Family: Software Product Line: Coregen Product Part: Coregen Product Version: 2.1 Problem Title: 2.1i COREGEN, MTI, VHDL: Required MTI commands for analyzing/compiling the CORE Generator VHDL models Problem Description: Urgency: standard General Description: Required ModelSIM/VHDL commands for analyzing/compiling the CORE Generator VHDL models extracted using get_models utility. Solution 1: As documented in Chapter 4 of the 2.1i CORE Generator User Guide, the required Modelsim commands to analyze the models are:     vlib xilinxcorelib     vmap xilinxcorelib ./xilinxcorelib     vcom -work xilinxcorelib <path_to_XilinxCoreLib_SOURCE_FILE_DIRECTORY>/<name_of_vhd_file>     ... Example:     vlib xilinxcorelib     vmap xilinxcorelib ./xilinxcorelib vcom -work xilinxcorelib /tools/xilinx/vhdl/src/XilinxCoreLib/prims_constants.vhd     ... Please refer to (Xilinx Solution #6250) for information on the order in which the models must be compiled. End of Record #6037 - Last Modified: 10/20/99 16:17

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