Answers Database
NGD2VER/NGD2VHDL: Creates netlists with undriven signals that produce 'X' outputs in simulation
Record #6071
Product Family: Software
Product Line: FPGA Implementation
Product Part: ngd_prep
Problem Title:
NGD2VER/NGD2VHDL: Creates netlists with undriven signals that produce 'X' outputs in
simulation
Problem Description:
Urgency: Standard
General Description:
NGD2VER or NGD2VHDL creates netlists with undriven signals
that produce 'X' outputs in simulation
Solution 1:
When running Ngd2ver or Ngd2vhdl with the "-r" option, the user
must also run ngdanno with the NGM file. Otherwise, do not specify
the "-r".
Solution 2:
Though the symptoms show in Ngd2ver or Ngd2vhdl, the problems
occurs upstream in Ngd_prep.
This has been fixed in the next release from Xilinx (2.1). However, the
current work-around is to set the environment variable XIL_PP_OPTIMIZE
setenv XIL_PP_OPTIMIZE ""
re-run Ngd2ver/Ngd2vhdl
End of Record #6071 - Last Modified: 04/20/99 10:46 |
