Answers Database
2.1i: Floorplanner: The IBUFG placment is not verified by DRC check
Record #6164
Product Family: Software
Product Line: Merged Core
Product Part: Floorplanner
Product Version: 2.1i
Problem Title:
2.1i: Floorplanner: The IBUFG placment is not verified by DRC check
Problem Description:
Urgency: Standard
General Description:
The Floorplanner DRC does not verify the IBUFG placement.
If placed in the wrong location, MAP fails with the following:
ERROR:xvkpu - The symbol clk.pad failed to join a blobal clock I/O
component as required. the symbol has a constraint (LOC=B() that
specifies an illegal physical site for the component.
Solution 1:
Please refer to Virtex Datasheet for the correct IBUFG locations:
http://support.xilinx.com/partinfo/databook.htm#virtex
OR
The following information is where the IBUFGs can go per package:
CS144: K7, M7, A7, A6
TQ144: 90, 93, 19, 16
PQ240/HQ240: 92, 89, 210, 213
BG256: Y11, Y10, A10, B10
BG352: AE13, AF14, B14, D14
BG432: AL16, AK16, A16, D17
BG560 : AL17, AJ17, D17, A17
FG256: N8, R8, C9, B8
FG456: W12, Y11, A11, C11
End of Record #6164 - Last Modified: 11/19/99 13:00 |
