Answers Database
FPGA Express: Signal or port name expected as actual in association element (VSS-806)
Record #6165
Product Family: Software
Product Line: Synopsys
Product Part: FPGA Express
Product Version: 3.1
Problem Title:
FPGA Express: Signal or port name expected as actual in association element (VSS-806)
Problem Description:
Urgency: Standard
General Description:
Port map declarations similar to the example described below may produce the following error:
Signal or port name expected as actual in association element (VSS-806)
P1: C5LCR port map (P=>VALUE, CLK=>CLK, L=>LOAD, R=>START, CO=>DONE);
where VALUE is a constant defined as follows:
CONSTANT VALUE: STD_LOGIC_VECTOR (5 DOWNTO 0) := "010010";
Solution 1:
The error may be produced due to a known issue whereby FPGA Express does not recognise
constants as acceptable connections to component ports. To resolve this problem see the
example provided.
Change the declaration of the constant to be a signal:
SIGNAL VALUE: STD_LOGIC_VECTOR (5 DOWNTO 0);
And after the "BEGIN" keyword assign the value intended to be the constant:
VALUE <= "010010";
End of Record #6165 - Last Modified: 09/24/99 09:19 |
