Answers Database
Synopsys FPGA Compiler: writes out absolete timing constrains in XNF (basnu:179)
Record #6192
Product Family: Software
Product Line: Synopsys
Product Part: FPGA Compiler
Product Version: 1999.05
Problem Title:
Synopsys FPGA Compiler: writes out absolete timing constrains in XNF (basnu:179)
Problem Description:
Urgency: Standard
General Description:
FPGA Compiler writes out timing constrains which may look like:
SYM, TSR22, TIMESPEC, TS186=P2S:75.00:reset, TS187=P2S:142.00:scan,
TS188=P2S:75.00:reset, TS189=P2S:75.00:start, TS190=P2S:75.00:reset,
TS191=P2S:142.00:scan,
P2S:75:reset is in absolete form and NGDBUILD (Translate) gives warnings:
WARNING:basnu:179 - Timespec "TS0 = C2S:75.00" is an obsolete form and will not be translated.
Solution 1:
Entering the following line in your .synopsys_dc_setup will fix this problem:
xnfout_constraints_per_endpoint = 0
End of Record #6192 - Last Modified: 05/26/99 10:49 |
