Answers Database
M1.5i/2.1i: How to utilize the Virtex secondary global clock routing
Record #6198
Product Family: Documentation
Product Line: FPGA Core
Product Part: Constraints Editor User Guide
Problem Title:
M1.5i/2.1i: How to utilize the Virtex secondary global clock routing
Problem Description:
Urgency: HOT
General Description:
Virtex devices have 24 secondary global clock routing
resources in addition to 4 global clock buffers. How does one utilize these?
Solution 1:
In M1.5i software release the Place and Router determines
the usage of these global clock routing resources.
In the current M2.1i software release the user will be able to use the
MAXSKEW constraint to tag nets to use the secondary global
routing resources in Virtex.
When a net with this MAXSKEW constraint is seen. PAR will place
the IOB that generates the signal on the top or bottom edge and the
route the signal using the secondary global clock routing.
The global clock buffers are used with BUFG components in the
design. The Global Clock Buffers only go to clocks in the Virtex
Device and not anywhere else.
An example:
NET any_net_name MAXSKEW = 7 ;
End of Record #6198 - Last Modified: 10/01/99 10:15 | 
