Answers Database
V1.5, V1.4 COREGEN, VERILOG, VHDL: .vhd and .v files produced by COREGEN are only for simulation.
Record #6260
Product Family: Software
Product Line: Coregen
Product Part: Coregen
Product Version: c1_5
Problem Title:
V1.5, V1.4 COREGEN, VERILOG, VHDL: .vhd and .v files produced by COREGEN are only for
simulation.
Problem Description:
Urgency: standard
General Description:
.vhd and .v files produced by COREGEN are only for functional simulation. They are NOT intended to
be
used for synthesis. Attempting to synthesize these models will give you suboptimal results. In mos
t
cases, simulation-specific constructs used in these models will prevent you from synthesizing them
altogether.
Implementation of the CORE Generator module is completely specified by the .EDN EDIF netlist
generated for it. For HDL design flows, this should be instantiated in your design as a "black box"
.
Solution 1:
Do not attempt to synthesize .v and .vhd files generated by CORE Generator.
End of Record #6260 - Last Modified: 04/22/99 09:42 |
