Answers Database
Logic Modelling: smartccn fails when using back-annotated EDIF created with .NGM file (error 11032: no package pin connected)
Record #6282
Product Family: Software
Product Line: Synopsys
Product Part: xsi-pgms
Problem Title:
Logic Modelling: smartccn fails when using back-annotated EDIF created with .NGM file (error
11032: no package pin connected)
Problem Description:
Urgency: Standard
General Description:
When trying to compile a back-annotated EDIF file with Smartccn, the following error may occur:
***** Error: The design port (data_out<7:0>) has no package pin connected.
1 error, 540 warnings, smartccn 11032
This error only occurs when two situations exist. First, the .NGM file must be used when creating
the back-annotated .NGA file, which is then used to create the back-annotated EDIF file.
Second, the original EDIF file created by the design entry tool must be written with busses intact.
If these two conditions exist, then when the back-annotated EDIF file is produced, the correlation
to the original design is done, pin assignments for busses will be lost. Since LMG needs all pin
assignments to create the SmartCircuit model, the error will occur.
Solution 1:
To work around this error, simply make sure that at least one of these to conditions are not met.
To instruct NGDANNO to not use the .NGM file (which is produced by MAP), open the Options
dialog in the Xilinx Design Manager (or Project Manager and click on "Edit Options..." next to the
Simulation Template. Under the General tab, deselect the box next to "Correlate Simulation Data
to Input Design".
-or-
Instruct your design entry tool to expand all bus signals into their component bits when writing the
EDIF file for implementation. How this is done will vary; consult your EDA tool documentation to
find out how.
End of Record #6282 - Last Modified: 10/25/99 11:50 |
