Answers Database
VCS: How to compile the 2.1i Simprim, LogiBLOX, Unisim, and Coregen HDL libraries?
Record #6330
Product Family: Software
Product Line: ViewLogic
Product Part: VCS
Problem Title:
VCS: How to compile the 2.1i Simprim, LogiBLOX, Unisim, and Coregen HDL libraries?
Problem Description:
Urgency: Standard
General Description:
To perform timing or post-synthesis functional Verilog simulation with the
Xilinx Alliance 2.1i tools, the Verilog-based Simprim models must be
compiled for use in the VCS simulator. If instantiated LogiBLOX, CORE
Generator and/or Unified library components are to be behaviorally
simulated, the LogiBLOX, CORE Generator and/or Unisim libraries must
be compiled as well.
The Xilinx Alliance software contains 2 types of Verilog simulation libraries
and Coregen contains one:
simprim - Library of generic simulation primitives
unisim - Library of Unified component simulation models
XilinxCoreLib - Coregen HDL Library. Please see (Xilinx Solution 7859)
for instructions on extracting this library.
Note: Tested with VCS 5.0.1a and later.
Solution 1:
# Compiling Unisims
vcs -Mdir=<compile_dir>/unisims_ver $XILINX/verilog/src/unisims/*.v \
$XILINX/verilog/src/glbl.v
# Compiling Uni3000
vcs -Mdir=<compile_dir>/uni3000 $XILINX/verilog/src/uni3000/*.v \
$XILINX/verilog/src/glbl.v
# Compiling Uni5200
vcs -Mdir=<compile_dir>/uni5200 $XILINX/verilog/src/uni5200/*.v \
$XILINX/verilog/src/glbl.v
# Compiling Uni9000
vcs -Mdir=<compile_dir>/uni9000 $XILINX/verilog/src/uni9000/*.v \
$XILINX/verilog/src/glbl.v
# Compiling Simprims
vcs -Mdir=<compile_dir>/simprims_ver $XILINX/verilog/src/simprims/*.v \
$XILINX/verilog/src/glbl.v
# Compiling Coregen
# Please see (Xilinx Solution 7859) for instructions on extracting this library.
vcs -Mdir=<compile_dir>/xilinxcorelib ./XilinxCoreLib/*.v
The -Mdir=<compile_dir> option specifies the pathname of a central
directory where you want VCS to write the generated files. This option
allows you to provide other members of your team with the generated
files for new or improved modules in a large design so that other
members don't have to compile those modules.
End of Record #6330 - Last Modified: 11/12/99 16:41 |
