Answers Database
SYNPLIFY: How to apply the BUFG attribute for XC9500 devices?
Record #6334
Product Family: Software
Product Line: Synplicity
Product Part: Synplify
Product Version: 5.0
Problem Title:
SYNPLIFY: How to apply the BUFG attribute for XC9500 devices?
Problem Description:
Urgency: Standard
Genaral Description:
How to apply the BUFG attribute for XC9500 devices within Synplify?
The BUFG attribute can be applied to any input buffer (IBUF), input pad
net, or internal net that drives a CLK, OE, or SR pin.
When applied to an input buffer or input pad net, th BUFG attribute maps
the tagged signal to a global net. When applied to an internal net, the
tagged signal is brought out to a global device control pin and then routed
to the connected internal control pins via a global net. This routing control
results in a higher speed for the affected control path as well as a reduction
in product term utilization. The cost for the improved performance is a
device input pin. The functional behavior remains unchanged.
The BUFG attribute has the following values: CLK, OE, or SR. Where CLK,
OE, and SR indicate clock, output enable, or set/reset, respectively.
In the A1.5 software, BUFG properties can be applied only to input ports.
This means that users who wish to control bus output enable from logic inside
the CPLD (all 9500 - 9500, 9500XL, 9500XV) will need to pass the signal out
to a device pin and back in before connecting to OE control points.
In A2.1i, the BUFG attribute can be applied directly to internal nets. The fitter
will then automatically route the signal through a "GTS" type (or other specified
type) I/O pin to control the OEs.
Solution 1:
// Verilog
module bufg_ex1 (din, clk, qout);
input [1:0] din;
input clk;
output qout;
reg [1:0] qout_int;
wire node /* synthesis syn_keep=1 xc_props="BUFG=OE" */;
always @(posedge clk)
qout_int = din;
assign node = &qout_int;
assign qout = (node)? qout_int[0] : 1'bz;
endmodule
Solution 2:
-- VHDL
library IEEE;
use IEEE.std_logic_1164.all;
library synplify;
use synplify.attributes.all;
entity bufg_ex1 is
port (din : in STD_LOGIC_VECTOR(1 downto 0);
clk : in STD_LOGIC;
qout : out STD_LOGIC);
end bufg_ex1;
architecture xilinx of bufg_ex1 is
signal qout_int : STD_LOGIC_VECTOR(1 downto 0);
signal node : STD_LOGIC;
attribute syn_keep of node : signal is true;
attribute xc_props of node : signal is "BUFG=OE";
begin
process (clk)
begin
if rising_edge(clk) then
qout_int <= din;
end if;
end process;
node <= qout_int(1) and qout_int(0);
qout <= qout_int(0) when (node = '1') else 'Z';
end xilinx;
End of Record #6334 - Last Modified: 10/08/99 13:01 |
