Answers Database Virtex CLKDLL HDL simulation: LOCKED signal doesn't lock if it's not in ps time resolution. Record #6362 Product Family: Software Product Line: FPGA Implementation Product Part: Unisim Problem Title: Virtex CLKDLL HDL simulation: LOCKED signal doesn't lock if it's not in ps time resolution. Problem Description: Urgency: Standard Problem Description: Virtex Unisim vhdl simulation on MTI, If using all default options, the LOCKED signal never goes hig h. Solution 1: Due to the wide range of frequencies the CLKDLL can take in from 25MHz on up, the Unisim and Simprim simulation models must account for the fastest clock frequency. Since the models use pico-seconds (ps) resolution, the signal edges may be missed if the users use any timescale that's larger than ps during simulation. In order to properly simulate CLKDLL, Users need to change the time resolution from ns to ps. In MTI, When invoking the vsim command, use the following command option: vsim -t ps End of Record #6362 - Last Modified: 06/22/99 10:31

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