Answers Database
Virtex timing simulation: DUTY_CYCLE_CORRECTION property on BUFGDLL in UCF file may not be seen by sim model
Record #6429
Product Family: Hardware
Product Line: Virtex
Product Part: Virtex General Hardware
Problem Title:
Virtex timing simulation: DUTY_CYCLE_CORRECTION property on BUFGDLL in UCF file may not be
seen by sim model
Problem Description:
Urgency: Standard
Problem Description:
Two of the CLKDLL-related properties can be put on the BUFGDLL element,
and they should control the behavior of the underlying CLKDLL simprim:
these are DUTY_CYCLE_CORRECTION and the new FACTORY_JF.
If these are specified in the UCF file, the new values will not be pushed down
to the underlying CLKDLL, and the simprim won't see them, so the simulation
will not correctly simulate these behaviors.
Solution 1:
To workaround this problem, use the following syntax in the ucf file:
INST <INST name> BUFGDLL/CLKDLL DUTY_CYCLE_CORRECTION=TRUE;
End of Record #6429 - Last Modified: 06/22/99 14:41 |
