Answers Database
2.1i: Timing: Offset out/before won't find clock period in calculating the timing values.
Record #6446
Product Family: Software
Product Line: Merged Core
Product Part: Timing
Problem Title:
2.1i: Timing: Offset out/before won't find clock period in calculating the timing values.
Problem Description:
Urgency: Standard
General Description:
Placed an OFFSET OUT/Before constraint on a path, but the values reported by TRACE/Timing Analyzer a
re coming up different than when I calculate them based up the equations in (Xilinx Solution #5489)
Solution 1:
An offset out/before constraint won't find the required clock
period if the output register does not clock anything. This
occurs when the register clocks a constant, and reset is
used to clear the register (a.k.a. a "one shot"). Since
there's no data path (with a period) associated with the
register, the tools cannot find the period and incorrectly
calculates the output offset.
One work around would be to enable path tracing of the
reset->clk setup checking, which is done by adding to the
pcf file the following:
ENABLE=reg_sr_q;
This will be fixed in a future release of the software.
End of Record #6446 - Last Modified: 08/03/99 16:01 |
