Answers Database
2.1i: TRCE/Timing Analyzer does not provide the ability to constrain the blockram halves separately.
Record #6448
Product Family: Software
Product Line: FPGA Implementation
Product Part: trce
Product Version: 2.1i
Problem Title:
2.1i: TRCE/Timing Analyzer does not provide the ability to constrain the blockram halves
separately.
Problem Description:
Urgency: Standard
General Description:
When constraining Block Ram, with TNM_NET placed on one
clock going to one of the halves. Why is the TNM applied to
both halves of the BlockRam?
Only the blockram half that is attached to that input or output
should be grouped.
An example:
NET "DIB0" TNM_NET = RAMS (DOB0) "BLOCKRAM_GRPB";
Solution 1:
This is the way that TNM works in the implementation tools. The
TNMs get pushed and identify the logical instances. The
BlockRam is a single instance in the logical world. The input pin
into which the TNM is traced does not affect how the instance
is tagged, nor does the output signal name.
The handling of the TNMs will change in a future release of the
software to support this issue.
Solution 2:
The solution is to manually edit the PCF file. If you go the xproj/ver1/rev1/designfile.pcf, you ca
n move the instance names into the appropriate timegrp you want.
End of Record #6448 - Last Modified: 11/08/99 10:55 |
