Answers Database
2.1i: TRCE/Timing Analyser: Skew not automatically accounted for on Virtex low skew clocks
Record #6449
Product Family: Software
Product Line: FPGA Implementation
Product Part: trce
Product Version: 2.1i
Problem Title:
2.1i: TRCE/Timing Analyser: Skew not automatically accounted for on Virtex low skew clocks
Problem Description:
Urgency: Standard
General Desciption:
When a clock signal is placed on the Low Skew Routing
Resources in VIrtex, the following warning appears;
WARNING:bastw:544 - Clock nets using non-dedicated
resources were found in this design.
Clock skew on these resources will not be automatically
addressed during path analysis. How can we turn on the
skew check for these signals?
Solution 1:
To create a timing report that analyzes clock skew for these
paths, run trce with the '-skew' option. Or to have PAR check
the skew on the design, set the environment variable
'XILINX_DOSKEWCHECK=1;"
An example of the TRCE command:
trce -skew design.ncd -o output.twr
End of Record #6449 - Last Modified: 06/29/99 17:13 |
