Answers Database LogiCORE PCI: What is the comply directory in the downloaded files? Record #6502 Problem Title: LogiCORE PCI: What is the comply directory in the downloaded files? Problem Description: Urgency: Standard General Description: There is a directory called comply in the downloaded version of the LogiCORE pci interface. What are the files in this directory used for? Note: This is not available for LogiCORE PCI Virtex Solution 1: The comply directory contains the compliance testbench. The PCI Compliance Checklist will provide more information on the tests and a copy of the Checklist can be found on pp. 5-35 to 5-55 in the 1999 Xilinx PCI Databook. The comply directories contain README or readme.txt files, hdl files and setup files (setup scripts for simulation tools and waveform display). The Compliance Testbench is set up to run with zero wait state and medium decode. To run the testbench with one wait state, edit the "stimulus.v" or "stimulus.vhd" file by:    A) search for the task "set_lc_opts"    B) to change to one wait state, change the second to the last parameter       from `on to `off (verilog or ver_exp) or from onn to off (vhdl or       vhdl_exp) Please consult the XLA Implementation Guide to find what tools and design flows are supported before performing simulation of the compliance testbench. ** Instructions to the PCI Compliance Testbenches ** 1. verilog flow: (Cadence Verilog-XL v.2.6.10)    a) Edit the testbnch.f file to reference to the correct simprim and       unisim libraries: update the <Xilinx_install_path> in following       lines of the testbnch.f to your Xilinx Install path.            -y <Xilinx_install_path>/verilog/src/UNI4000X            -y <Xilinx_install_path>/verilog/data    b) Run the testbench simulation using the command            verilog -f testbnch.f       A "waves.shm" directory is created to display the simulation waveform.       The waveform display options are specified by the simwave.sv file.    c) View the output waveform using SIMWAVE command            simwave &    d) View the output file waves.tbl for simulation result. 2. vhdl flow: (Synopsys VSS 1998.02)    a) Edit the .synopsys_vss.setup file to map the design_library_names (SIMPRIMVSS       and UNISIMVSS) to your host name directories.            SIMPRIMVSS : ./SIMPRIMVSS            UNISIMVSS : ./UNISIMVSS    b) The testbnch.init file will analyze and simulate the testbench. When invoked,       it creates new WORK, SIMPRIMVSS and UNISIMVSS directories, then it analyzes       and simulates the testbench.       You need to specify the correct simprim and unisim libraries in your environment.       Replace "$XILINX" with your Xilinx Install path.       Note: Analyze the unisim_VPKG.vhd file provided in the comply directory since          this file contains fix not in the unisim_VPKG.vhd file in M1.5isp2.    c) Run the simulation using the command            ./testbnch.init       A "TESTBNCH.ow" file will be created and can be used with the WAVES Synopsys       waveform viewer. A "testbnch.inc" and "testbnch.wfm" have been included in       this directory to generate waveforms for the relevant Testbench signals.    d) View the output file waves.tbl for simulation result. 3. ver_exp flow: (ModelSim PE/Plus v4.7h)    a) Edit the testbnch.f file to reference to the correct Verilog simulation libraries.       The two lines start with "-y" in the testbnch.f file need to be replaced by the       following,            -y <Xilinx Install Path>\verilog\src\UNI4000X            -y <Xilinx Install Path>\verilog\data    b) Create a working directory called work            > vlib work    c) Run the simulation, first compile all the files using the command            > vlog -f testbnch.f    d) Simulate the top-level module "testbnch"            > vsim testbnch       There are expected warnings to the testbnch.v file about the "$shm_open" and       "$shm_probe" tasks. These system tasks are used in Verilog-XL simulation and       the warnings are not harmful to the MTI simulation.    e) View all the required windows for debugging,            > view source signals structure list wave    f) Display the reference signals, defined in the wave.do macro, to the Wave window,            > do wave.do    g) Run the simulation            > run -all    h) View the output file waves.tbl for simulation result. 4. vhdl_exp flow: (ModelSim PE/Plus v4.7h)    a) Edit the setup file, modelsim.ini file       If you want to reference to the existing simprim and unisim       libraries, edit the simprim and unisim paths in the       modelsim.ini file to reference to the correct library       locations in your environment and skip to (4d).       If you want to compile the two libraries, delete the simprim       and unisim path reference statements in the modelsim.ini file. b) Compile the Xilinx simulation library under the MTI simulator. i. create simprim directory > vlib simprim ii. map the working directory to simprim > vmap work simprim iii. compile Xilinx specific simulation primitives into simprim > vcom <Xilinx Install Path>\vhdl\src\simprims\simprim_VPACKAGE.vhd > vcom <Xilinx Install Path>\vhdl\src\simprims\simprim_VCOMPONENTS.vhd > vcom <Xilinx Install Path>\vhdl\src\simprims\simprim_VITAL.vhd iv. add the line "simprim = ./simprim" in the modelsim.ini file    c) Compile the Xilinx unisim library under the MTI simulator. i. create unisim directory            > vlib sim       ii. remap the working directory to unisim            > vmap work unisim       iii. compile Xilinx unisim primitives into unisim            > vcom <Xilinx Install Path>\vhdl\src\unisims\unisim_VCOMP.vhd            > vcom <Xilinx Install Path>\vhdl\src\unisims\unisim_VPKG.vhd            > vcom <Xilinx Install Path>\vhdl\src\unisims\unisim_VITAL.vhd       iv. add the line "unisim = ./unisim" in the modelsim.ini file    d) Create a work directory and remap the working directory to work.            > vlib work            > vmap work work    e) Invoke the testbench, compile all the files using the following command            > vcom -explicit -f testbnch.init    f) Simulate the top-level module "testbnch"            > vsim testbnch    g) View all the required windows for debugging,            > view source signals structure list wave    h) Display the reference signals, defined in the wave.do macro, to the Wave window,            > do wave.do    i) Run the simulation            > run 268155 ns    j) View the output file waves.tbl for simulation result. End of Record #6502 - Last Modified: 08/25/99 15:55

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