Answers Database
SYNPLIFY: Force GSR on Virtex designs does not generate a STARTUP_VIRTEX cell
Record #6583
Product Family: Software
Product Line: Synplicity
Product Part: Synplify
Product Version: 5.0
Problem Title:
SYNPLIFY: Force GSR on Virtex designs does not generate a STARTUP_VIRTEX cell
Problem Description:
Urgency: Standard
General Description:
When compiling a design for a Virtex device, the force GSR
option does not generate the STARTUP_VIRTEX cell in the EDIF
netlist. Typically, this force GSR option should infer the
STARTUP_VIRTEX cell.
Solution 1:
For Virtex designs, Xilinx strongly recommend for designers to design their own
reset network instead of using GSR because the secondary routing for reset
is much faster than GSR. You could use a STARTUP_VIRTEX cell to reset the
entire design, but using your own reset is the preferred way to do it.
On the Virtex device the GSR routing can be slower than routing of "manual"
reset lines to latches. Therefore it can be advantageous to not instantiate the
STARTUP_VIRTEX block in the Virtex device. Of course the STARTUP_VIRTEX
block can be manually instantiated. The default therefore should be no GSR
forcing which is why it will not produce a startup block (preventing inadvertant
GSR usage).
End of Record #6583 - Last Modified: 05/20/99 17:33 |
