Answers Database
LOGIBLOX, SIMPRIM, 4K: Timing simulation of Counter does not work, all outputs are "X"
Record #6584
Product Family: Software
Product Line: FPGA Implementation
Product Part: logiblox
Problem Title:
LOGIBLOX, SIMPRIM, 4K: Timing simulation of Counter does not work, all outputs are "X"
Problem Description:
Urgency: standard
General Description:
Cannot simulate logiblox counter after post route. All the outputs are "X".
Although GSR is toggled at the beginning of a timing simulation, and all
inputs are defined at the beginning of the simulation, the outputs are
always "X" and never change.
Functional simulation works fine using the same testbench.
Solution 1:
The problem is due to not asserting GSR for a sufficiently long time.
You must assert GSR for at least 100ns.
End of Record #6584 - Last Modified: 05/20/99 15:37 |
