Answers Database
2.1i: FPGA Editor: Excessivly long load time for Virtex 1000
Record #6600
Product Family: Software
Product Line: Merged Core
Product Part: FPGA Editor
Problem Title:
2.1i: FPGA Editor: Excessivly long load time for Virtex 1000
Problem Description:
Urgency: Standard
General Description:
When invoking FPGA Editor there is an excessively long load time for large
designs (v1000 for example).
Is there any way to speed up the loading of the design?
Solution 1:
When FPGA Editor takes a long time to load, one can
change inte fpga_editor.ini file to either turn off the stub
triming or turn off the routing display. To accomplish this
for a particular design do the following steps:
1. Open the fpga_editor.ini file (found in $XILINX\data)
2. Go to the bottom of the .ini file in the '#Set what items
will be initially displayed' section.
3. Add the line 'setattr main stub-trim off' in the section or
change 'setattr layer routes view on' to 'setattr layer
routes view off'.
4. Save the file as 'fpga_editor_user.ini' in the
'design\ver\rev' directory.
5. Open up the design in Design Manager.
6. Right click on the design name in the main Design
Manager window.
7. Select 'Properties'.
8. Push the 'Revision List...' button.
9. Under the 'Filename:' data entry field find your
fpga_editor_user.ini file in the 'design\ver\rev'
directory.
10. Push the 'Set' button.
11. Push the 'OK' button.
The above steps will allow fpga_editor_user.ini file to be
used only with the appropriate design until changed. The
file will be copied from revision to revision regardless of
version.
This will be fixed in a future release.
End of Record #6600 - Last Modified: 06/30/99 08:48 |
