Answers Database JTAG BSDL - What are the Boundary Scan IDCODES for Virtex FPGAs? Record #6635 Problem Title: JTAG BSDL - What are the Boundary Scan IDCODES for Virtex FPGAs? Problem Description: Urgency: Standard General Description: What are the IDCODES for each Virtex FPGA? Solution 1: The IDCODE is described in the BSDL file. There is a unique IDCODE for each part family member and Mask revision. The general format is: Revision | Part Number | Manufacturer ID | 1 bit: 31-28 | 27-12 | 11-1 | 0 in general: XXXX 0000011 YYYYYYYYY 0000 1001 001 1 The revision code will be different for every mask revision, so the IDCODE lists it as a don't care for this field. The # of rows would be 32 for a V300, 64 for a V1000, etc. For example, the V300 IDCODE from the BSDL file is: attribute IDCODE_REGISTER of XCV300_PQ240 : entity is       "XXXX" & -- version       "0000011" & -- family       "000100000" & -- array size       "00001001001" & -- manufacturer       "1"; -- required by 1149.1 so the ID code is: XXXX 0000011 000100000 0000 1001 001 1 More information can be found in the Data Sheets as well as XAPP139 http://support.xilinx.com/xapp/xapp139.pdf End of Record #6635 - Last Modified: 01/10/00 19:49

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